Technology

Analysis-Huawei bets on speed over shrinking transistors to sidestep US chip sanctions

Asia / China0 views1 min
Analysis-Huawei bets on speed over shrinking transistors to sidestep US chip sanctions

Huawei introduced the Tau Scaling Law, a new chip design principle focused on improving signal speed rather than shrinking transistors, aiming to bypass U.S. sanctions blocking advanced EUV machines. Critics argue the approach resembles existing 3D stacking and packaging technologies, while Huawei claims it offers unique advantages in efficiency and clock speeds over the next decade.

Huawei has unveiled a new chip design strategy called the Tau Scaling Law, prioritizing signal transmission speed over transistor shrinkage to evade U.S. sanctions. Since 2019, China has been restricted from importing ASML’s advanced EUV lithography machines, limiting its ability to follow Moore’s Law and compete with global leaders like Taiwan’s TSMC in producing smaller, more powerful chips. The core technique, LogicFolding, stacks logic, analog, and memory circuits into tightly connected layers, potentially improving chip density, efficiency, and clock speeds. Huawei’s president, He Tingbo, stated the move addresses both an impending physical limit to Moore’s Law and the earlier sanctions-induced setback. However, industry experts note that reducing latency has long been part of chip design, with TSMC already using advanced 3D stacking and packaging for nearly a decade. TSMC’s SoIC technology and memory manufacturers like SK Hynix and Samsung have also adopted multi-layer stacking to enhance AI chip performance and power efficiency. Huawei claims LogicFolding surpasses conventional methods by finely splitting critical logic paths across layers, but analysts warn of challenges like increased power density, overheating risks, and production costs. Huawei’s roadmap acknowledges the need for new semiconductor design tools and heat management solutions for devices ranging from smartphones to AI data centers. The shift from chip-level optimization to system-level time-based design will also demand updates from electronic design automation vendors, according to He Tingbo. While Huawei frames this as a breakthrough, Nvidia CEO Jensen Huang dismissed it as a threat to TSMC, emphasizing the latter’s long-standing expertise in advanced packaging. The approach’s success hinges on overcoming technical hurdles and proving its superiority over existing methods in real-world applications.

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