Technology

SK hynix’s iHBM tackles heat choking next-gen HBM

Asia / South Korea0 views1 min
SK hynix’s iHBM tackles heat choking next-gen HBM

SK hynix introduced iHBM, a cooling-integrated packaging technology for high-bandwidth memory (HBM) chips, designed to reduce thermal resistance by over 30% and support next-gen AI workloads. The technology will debut with HBM5 around 2029-2030, aligning with industry shifts to hybrid bonding, while SK hynix faces surging demand exceeding its production capacity.

SK hynix unveiled iHBM, a new packaging technology embedding silicon-based cooling channels directly into high-bandwidth memory (HBM) chips to address heat buildup in AI applications. The innovation targets the hottest junction between memory and processor, using silicon’s conductive properties to dissipate heat without disrupting electrical pathways. The company claims iHBM reduces thermal resistance by over 30%, maintaining performance under high temperatures, and is compatible with existing package layouts via its Advanced MR-MUF process. The solution is slated for HBM5, expected to launch between 2029 and 2030, coinciding with the industry’s adoption of hybrid bonding—a method replacing traditional copper bump structures. SK hynix emphasized iHBM’s readiness for mass production, leveraging its expertise in memory design and advanced packaging. Lee Kang-wook, head of package development, stated the technology combines these capabilities to minimize heat in next-generation memory stacks. Demand for SK hynix’s HBM currently outstrips production capacity, with customer orders exceeding the company’s output over the next three years. The first quarter of 2026 saw record financials: 52.6 trillion won in revenue and a 72% operating margin, driven by AI-driven memory demand. Despite Samsung Electronics reclaiming the top spot in overall DRAM revenue in Q4 2025, SK hynix retained a dominant 57% share of the HBM market. The announcement highlights SK hynix’s strategic focus on overcoming thermal bottlenecks in AI infrastructure, ensuring scalable memory solutions for future workloads. The integration of cooling into the chip package aligns with broader industry efforts to push HBM performance beyond current limitations.

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